Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use one-transistor memory cells. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. For example, a row of memory cells might be those memory cells commonly coupled to an access line. Columns of the array might include strings (often termed NAND strings) of memory cells connected together in series between a pair of select transistors, e.g., a source select transistor and a drain select transistor. Each source select transistor is connected to a source, while each drain select transistor is connected to a data line, such as bit line.
A “column” may refer to memory cells that are commonly coupled to a data line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. Note, for example, that for an array having a plurality of memory blocks, a string of memory cells of each memory block might be selectively coupled to a common data line through a drain select transistor.
A row of memory cells can, but need not, include all memory cells commonly coupled to an access line. A row of memory cells might include every other memory cell commonly coupled to an access line. For example, memory cells commonly coupled to an access line and selectively coupled to even data lines may be a row of memory cells, while memory cells commonly coupled to that access line and selectively coupled to odd data lines may be another row of memory cells. Other groupings of memory cells commonly coupled to an access line may also define a row of memory cells. For certain memory devices, all memory cells commonly coupled to a given access line might be deemed a physical row, while those portions of the physical row that are read during a single read operation or programmed during a single program operation (e.g., even or odd memory cells) might be deemed a logical row, sometimes referred to as a page.
Some memory devices might include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array might include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., coupled in series, between a source and a data line. The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
Memory cells, such as non-volatile memory cells, can be programmed to have multiple bits, e.g., during multilevel programming. A memory cell having multiple bits might sometimes be referred to as a multilevel memory cell (e.g., MLC), for example. A respective data value (e.g., as represented by a bit pattern) may be assigned to each of a plurality of levels, where each level corresponds to a respective data state.
Each level (e.g., data state) may be characterized by a corresponding distinct range of threshold voltages (Vts) of a plurality of distinct ranges of threshold voltages that can be stored on the multilevel memory cells. A margin (e.g., a certain number of volts), such as a dead space, may separate adjacent threshold-voltage ranges, e.g., to facilitate differentiating between data values. This technology permits the storage of two or more bits per memory cell. The number of program levels used to represent a bit pattern of N bits may be 2N, for example.
Multilevel programming might involve programming a row of multilevel memory cells at a time. For example, programming voltage pulses might be applied to the access line commonly coupled to the row of multilevel memory cells in order to shift the threshold voltages of the multilevel memory cells. During the programming, memory cells of the row to be programmed to lower program levels (e.g., lower threshold-voltage ranges) usually reach their assigned threshold voltage before other memory cells coupled to the same access line that are to be programmed to higher program levels reach their assigned threshold voltages. This can cause what is known in the art as program disturb issues that can occur when the memory cells in the same row that are already programmed to the lower levels (e.g., threshold-voltage ranges) and/or in an adjacent row of memory cells that are already programmed to the lower levels continue to experience the effects of additional programming pulses used to program remaining memory cells to the higher threshold-voltage ranges.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing multilevel programming techniques.